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Re: Differential ADC (ADC1-ADC2)

Posted: Fri Sep 22, 2017 2:22 am
by victor_pv
mrburnette wrote:
Sun Sep 17, 2017 10:02 pm
Recall that the official Maple mini had separate analog and digital ground planes.
Baite (&others) went cloning with a dual-sided board ... hence the increased analog noise.

And the original had 4 layers vs 2 in the clones too.

Re: Differential ADC (ADC1-ADC2)

Posted: Fri Sep 22, 2017 3:13 am
by RogerClark
I'm not sure if @pito's original schematic is going to yield useful results.

Aren't both ADC inputs going to suffer the same amount of common mode noise at the same time ?

I see that the 2 inputs have a resistor between them, but the value has not been specified, and even if there was a high value resistor, I'm don't understand how that would help, it would just form a voltage divider with the input impedance on the ADC2

I can see if ADC2 is supplied with a clean reference voltage, that any changes in value have to be associated with supply noise, and this DeltaV from the actual reference voltage value, could be used to to remove noise from ADC1

But this presumes that supply noise has an equal numerical value on low input voltages e.g 0.3V as on high input voltages e.g. 3.0V

On a vaguely related topic. I've been experimenting with a HB100 doppler radar module, which has a very small signal output, of just a few mV, hence a multi stage opamp amplifier is used to increase the voltage output range to 0 - 3.3V

However, when I supply the HB100 and amplifier from the 3.3V pin on the BluePill, the amount of supply noise to the HB100 + amp, causes major problems and makes it unusable.

My current plan is to rebuild using an opamp with better common mode rejection, but also to supply from the 5V pin on the BP, and use a separate regulator for the 3.3V rail needed by the HB100, in the hope that gets around the supply noise problem

Re: Differential ADC (ADC1-ADC2)

Posted: Fri Sep 22, 2017 8:45 am
by stevestrong
My experience is that the only way you get reasonable ADC values (having low noise +/-1 bit (!!), non-differential input) is to feed the BP from a battery (~3.6V).
Then I used to send the sampled values over SPI to another BP, having only GND and the SPI lines common for both BPs.
Important is to send the sampled values between sample periods:
- ADC (simultaneous dual) sample
- send data
- ADC (simultaneous dual) sample
- send data
and so on, so that no digital noise (SPI toggling) will affect the sampling.

Re: Differential ADC (ADC1-ADC2)

Posted: Sun Sep 24, 2017 4:42 pm
by Pito
I'm not sure if @pito's original schematic is going to yield useful results.
The schematics above is not a "schematics", it is rather a picture :) to depict the diff. Imagine all the wires there are complex elements (RLC) :)

The ADC1 and ADC2 have got the same VCC and VGND (an assumption which may not be valid in very detail), so the jumps on VCC and VGND rails (outside the chip) are for both ADCs the same (ok, we may start to discuss how the ADCs are connected to Vcc and Vgnd on the silicon..) - thus the differential mode will cancel the noise jumps.
I would be happy to try it on various boards, when a piece of code for simultaneous sampling of ADC1 and ADC2 is handy somewhere (here it must be really the "simultaneous mode", a delay by a single clock would be a showstopper of such an exercise).

Re: Differential ADC (ADC1-ADC2)

Posted: Sun Sep 24, 2017 10:11 pm
by RogerClark
I would try supplying ADC2 with a stable reference voltage, e.g. even if this is just vcc via a resistor divider with a smoothing cap.

Then if you compare the last reading in ADC2 with the current reading, any difference should be he supply noise.