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Measuring Vxx with zero load Divider

Posted: Tue Jan 10, 2017 11:20 pm
by Pito
For people who want to save energy - a voltage divider which does not load the Vxx (V1).
Vxx could be any reasonable voltage, not only 5V as depicted above.
The Voltage divider does not load the Vxx, only during a measurement.
The resistors in the Divider could be of any value you need to fit into ADC range.
Nice to have when you talk uA power consumption and 1-10k source impedance for fast and reliable ADC :)
Provided as-is, no warranties of any kind are provided, use at your own risk :)
The sketch is easy to create, left as an exercise for the readers :)
Vxx Trick.JPG
Vxx Trick.JPG (15.99 KiB) Viewed 122 times

Re: Measuring Vxx with zero load Divider

Posted: Tue Jan 10, 2017 11:45 pm
by ahull
That is a neat trick. I wonder how high a voltage on the V1 input you could get away with. Switchable attenuators for the pig-o-scope are one use case that comes to mind.

Re: Measuring Vxx with zero load Divider

Posted: Wed Jan 11, 2017 12:14 am
by RogerClark

I just tried to model this in LTSpice but I get strange results

I thought I'd turn on the control signal for 100 microseconds, (actually I used a square wave of period 200 microseconds), but the waveform I get on the middle of the divider is a series of increasing voltage pulses

Maximum voltage I get on the middle of the divider (for 5V input ) is 600mV

I've attached my LTSpice file (perhaps I made a mistake)

Re: Measuring Vxx with zero load Divider

Posted: Wed Jan 11, 2017 7:44 am
by Pito
It works such you toggle the Pinx (output) from 1 to 0.
That opens the Q1 for
time t = aprox R3 * C1.
During that time you have to provide ADC. As it takes say 1us for STM32, you may try with
R3 = 10k C1 = 4n7-10n
to get t = say 100usecs. You may try even smaller t. The goal is to get the smallest t while the measured ADCin is still stable/precise.

After the measurement you do nothing, the C1 discharges, Q1 will be closed and Vxx and the Divider (say 9k/1k) will be switched off from MCU. No current drained.
Good if you want to measure Vxx = 3V on a CRxxxx coin battery from time to time.. Or something like that.

PS: mind the t changes with Vxx a little bit. You need a logic Q1 pmosfet with lowest level threshold, ie. 1.5V.

Below simulation: it took 1usecs to get the ADC Vin stable. And it lasts for 30usecs stable. You do ADC there. R4 and C2 are parasitic for simulation only.
I do not have such low threshold logic level Pmosfet model for simulation, so I used power mosfet instead (not good, it has high threshold voltage and big gate capacitance).
Zero power DIVIDER.JPG
Zero power DIVIDER.JPG (66.72 KiB) Viewed 101 times

And the situation with 30V Vxx, and the divider 9k/1k.
Zero power DIVIDER 3.JPG
Zero power DIVIDER 3.JPG (77.72 KiB) Viewed 98 times

As you can see from that picture:

1. the turquoise blue transitor's Gate-Source voltage decreases by the (-)5V difference created by the 1->0 pulse at Pinx (green). For that Pmos it means it "opens" itself as the pulse peak is higher than its G-S threshold voltage.

2. the yellow voltage at the ADC's input is 3V. It lasts for ~40us stable. Enough time to measure.
So the whole measurement process you load the Vxx with the Divider (and capacitive C1 current) could be for example 5usecs (with a smaller R3 or C1, toggle Pinx, wait 1usecs till ADC voltage stabilize, do ADC in 1us..). Needs to be elaborated in real life, however :)

3. during the time Vxx is connected to and the ADC's input voltage is stable it takes 3.5mA off the Vxx, 200usecs from the start the Vxx current drops to 80uA, after 1.5ms the Vxx current reaches 7nA..

PS: from that picture you may see the threshold voltage of the pmosfet used in the simulation is about -3V. Therefore that transitor will most probably not work with 3.3V 1->0 Pinx pulse. You need a pmosfet with "logic level threshold" - those are 1.2-1.5V threshold transistors to work with 3.3V levels. Consult your datasheets.

And the ADC input voltage at the beginning of the cycle and after 40usecs.
V1: 2.9996V
V2: 2.9967V
Zero power DIVIDER 4.JPG
Zero power DIVIDER 4.JPG (33.26 KiB) Viewed 91 times

Re: Measuring Vxx with zero load Divider

Posted: Wed Jan 11, 2017 2:16 pm
by mrburnette
For those not wanting to complicate things too much, the online Falstad Circuit Simulator is easy to use.
CircuitSimulator.jpg (46.02 KiB) Viewed 83 times

Code: Select all

$ 1 0.000005 40.34287934927352 99 5 50
f 208 160 144 160 1 1.5 0.02
R 144 144 144 96 0 0 40 5 0 0 0.5
c 208 160 288 160 0 0.000009999999999999999 4.973901531836262
r 144 176 144 272 0 10000
r 144 272 144 352 0 10000
g 144 352 144 400 0
w 144 272 288 272 0
R 336 112 336 80 0 0 40 5 0 0 0.5
w 208 160 208 112 0
r 336 112 208 112 0 100000
x 312 275 421 278 0 24 Analog Tp
R 288 160 368 160 0 2 40 5 0 0 0.5
o 0 64 0 2083 5 0.4 0 -1 0

Current in the Vdivider is 50nA to 250uA

Re: Measuring Vxx with zero load Divider

Posted: Wed Jan 11, 2017 3:12 pm
by Pito
@mrburnette: Your C1=10uF, shall be 10nF.. Try my second example with Vxx=30V and 9k/1k divider (R3=10k, C1=10nF) if you get similar results as I got.
Mind there is a current via capacitor C1 as well (during charging/discharging), not only via the divider.

Re: Measuring Vxx with zero load Divider

Posted: Wed Jan 11, 2017 7:46 pm
by RogerClark
I tried the circuit again in LTSpice, but it still didn't give the same results.

I get a big volt drop across the FET , and I don't know why.

But I seem to have issues with FETs in LTSpice, which I need to fix sometime.

Re: Measuring Vxx with zero load Divider

Posted: Wed Jan 11, 2017 9:43 pm
by Pito
@Roger: Works fine your simulation :)
With some fixes, of course :)
OMG that graphics, icons, like a children's toy :)
Red - Gate, Blue - mid of the Divider, Green - Pinx pulse
Roger LTspice Zero Power DIV.JPG
Roger LTspice Zero Power DIV.JPG (80.51 KiB) Viewed 60 times

Here Red - mid of the divider - my second example with 30V and 9k/1k divider.
Roger LTspice Zero Power DIV 2.JPG
Roger LTspice Zero Power DIV 2.JPG (98.48 KiB) Viewed 53 times

This is with R=100k and C=3.3nF - maybe it is a better variant as the current via the C will be much lower.
Roger LTspice Zero Power DIV 3.JPG
Roger LTspice Zero Power DIV 3.JPG (87.65 KiB) Viewed 51 times

Re: Measuring Vxx with zero load Divider

Posted: Wed Jan 11, 2017 10:28 pm
by RogerClark
Thanks Pito

I will try it when I get home

Re: Measuring Vxx with zero load Divider

Posted: Wed Jan 11, 2017 11:12 pm
by RogerClark
Pito can you zip and post your simulator (asc) file


No need.

What the problem seemed to be is that the FET needed to have its type set, ie so it modelled a real device, rather than a theoretical "perfect" FET.
I'm not sure why this is, as normal bipolar transistors in LTSpice are OK using the theoretical model most of the time (they seem to be a good close match to real world bipolars)


@Pito, which simulator do you normally use ?
I thought LTSpice had a good reputation for accuracy and flexibility, with its main drawback being its very clunky user interface