SoftPWM via DMA and no CPU cycles

Post your cool example code here.
victor_pv
Posts: 1734
Joined: Mon Apr 27, 2015 12:12 pm

Re: SoftPWM via DMA and no CPU cycles

Post by victor_pv » Mon Jul 10, 2017 5:58 pm

BTW, there is a function to do this:
TIMER2_BASE->DIER = TIMER_DIER_CC3DE;

Since it's an inline shouldn't take many instructions and makes the code more portable between timers

Code: Select all

/**
 * @brief Enable a timer channel's DMA request.
 * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL
 * @param channel Channel whose DMA request to enable.
 */
static inline void timer_dma_enable_req(timer_dev *dev, uint8 channel) {
    *bb_perip(&(dev->regs).gen->DIER, channel + 8) = 1;
}
Furthermore, you don't need to use a channel CC to trigger the DMA. The update event (when the timer reaches the overflow there is an update event) could be used for that. There was no function in the core for that, but we just added it recently. If you use that, you dont need to set up the CC, and can keep using the channels for normal PWM if you want (at *resolution* times faster speed than the soft one, so it can provide a timebase if one is needed at the frequency of DMA refresh.

Code: Select all

/**
 * @brief Enable a timer's update DMA request
 * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL
 */
static inline void timer_dma_enable_upd_req(timer_dev *dev) {
    *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_UDE_BIT) = 1;
}
This may have drawbacks though, I believe when you change the ARR and call timer.update it will also generate an update event, and so 1 DMA transfer.

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