stm32f429 SRAM + ext SRAM + TFT 16bit with DMA

What are you developing?
User avatar
diger67
Posts: 30
Joined: Thu Sep 10, 2015 12:13 am
Location: Russia, Sankt- Piterburg

stm32f429 SRAM + ext SRAM + TFT 16bit with DMA

Post by diger67 » Mon Jan 16, 2017 1:59 am

Good day. I try to implement the idea for the removal of information on the TFT screen is pre-recorded in the external memory, and then write it in the TFT using DMA. That's what has happened to make.

https://youtu.be/2yn_j_dLoy4
https://youtu.be/wYmzSF-hkl0
https://youtu.be/OnpP7y9HBw4
https://youtu.be/nulBXs08cjs
https://youtu.be/G_QIx3eDdDc
https://youtu.be/oycXAoZCJm4
Last edited by diger67 on Thu Jan 19, 2017 3:35 pm, edited 1 time in total.

User avatar
diger67
Posts: 30
Joined: Thu Sep 10, 2015 12:13 am
Location: Russia, Sankt- Piterburg

Re: stm32f429 SRAM + ext SRAM + TFT 16bit with DMA

Post by diger67 » Thu Jan 19, 2017 8:37 am

This solution allows you to prepare a copy of the display area in the external memory and display screen one dump. It also allows you to realize the function of the virtual layers. With sufficient external memory can store several preformed screen screenshots and print them on demand.

stevestrong
Posts: 1447
Joined: Mon Oct 19, 2015 12:06 am
Location: Munich, Germany

Re: stm32f429 SRAM + ext SRAM + TFT 16bit with DMA

Post by stevestrong » Thu Jan 19, 2017 7:53 pm

Without browsing through the videos, could please describe what kind of TFT do you use? Spi or parallel?

User avatar
diger67
Posts: 30
Joined: Thu Sep 10, 2015 12:13 am
Location: Russia, Sankt- Piterburg

Re: stm32f429 SRAM + ext SRAM + TFT 16bit with DMA

Post by diger67 » Thu Jan 19, 2017 11:43 pm

Used TFT connected in parallel 16-bit bus. Probably it is possible to SPI and use. I did not think long about this question.

stevestrong
Posts: 1447
Joined: Mon Oct 19, 2015 12:06 am
Location: Munich, Germany

Re: stm32f429 SRAM + ext SRAM + TFT 16bit with DMA

Post by stevestrong » Fri Jan 20, 2017 9:19 am

So you actually use 16 bit bus for data and another 8 bit for control signals, right? I think you need two different DMAs for this.

How do you synchronize the two DMAs? Triggered by the same counter?

User avatar
RogerClark
Posts: 6401
Joined: Mon Apr 27, 2015 10:36 am
Location: Melbourne, Australia
Contact:

Re: stm32f429 SRAM + ext SRAM + TFT 16bit with DMA

Post by RogerClark » Fri Jan 20, 2017 9:57 am

stevestrong wrote:So you actually use 16 bit bus for data and another 8 bit for control signals, right? I think you need two different DMAs for this.

How do you synchronize the two DMAs? Triggered by the same counter?
@stevestrong

That was my though as well.

Its not just data that needs to be DMA'ed, normally control signals need to be toggled as well.

If it was just 8 bit data, you could use a 16 bit data width DMA to GPIO and use the upper 8 bits for control signals, but if its 16 bit data its not as easy.

I suspect you'd need a FPGA to do this

User avatar
Pito
Posts: 1387
Joined: Sat Mar 26, 2016 3:26 pm
Location: Rapa Nui

Re: stm32f429 SRAM + ext SRAM + TFT 16bit with DMA

Post by Pito » Fri Jan 20, 2017 11:51 am

A tft display with 16bit data shall be connected via FSMC. FSMC is the interface for a 16bit tft..
And it will be memory mapped. Then you can use DMA.
There are examples somewhere, afaik.
Search "stm32 FSMC TFT display" on the web..
Pukao Hats Cleaning Services Ltd.

User avatar
diger67
Posts: 30
Joined: Thu Sep 10, 2015 12:13 am
Location: Russia, Sankt- Piterburg

Re: stm32f429 SRAM + ext SRAM + TFT 16bit with DMA

Post by diger67 » Fri Jan 20, 2017 7:05 pm

stevestrong wrote:So you actually use 16 bit bus for data and another 8 bit for control signals, right? I think you need two different DMAs for this.

How do you synchronize the two DMAs? Triggered by the same counter?
According to the DMA transferred data only, write to the control register is a function of the type * (uint16_t *)ADDR_DATA = dt, * (Uint16_t *) ADDR_CMD = cmd.

Code: Select all

#define LCD_BANK_ADDR				(uint32_t)0x64000000
#define LCD_RAM_ADDR				(uint32_t)0x64200000	//A20 16 bit
#define ADDR_CMD 					*(uint8_t*)LCD_BANK_ADDR
#define ADDR_DATA 				*(uint16_t*)LCD_RAM_ADDR

//------------------------------------
void LCD_Write_COM(uint8_t cmd)
{
		ADDR_CMD = cmd;
}
//------------------------------------
void LCD_Write_DATA(uint16_t dt)
{
		ADDR_DATA = dt;
//		TFT_Delay(1);
	__asm{nop
				nop}
				
}

Code and more optimized algorithm, there are many issues in stability, changed the external memory with 55ns to 12ns recently. It also brought about changes in the code. The biggest problem is to set the memory timings and TFT, or otherwise breaks the synchronization or the image appears distorted. Therefore, in no hurry to spread the code.

User avatar
diger67
Posts: 30
Joined: Thu Sep 10, 2015 12:13 am
Location: Russia, Sankt- Piterburg

Re: stm32f429 SRAM + ext SRAM + TFT 16bit with DMA

Post by diger67 » Tue Jan 24, 2017 2:17 pm

Replacing the external memory has given result. The image is output stably without distortion. Came stm32f446, will be connected by 25Qxxx on QSPI and transfer to all arrays of constants. The next step in the transient stm32f746.

stevestrong
Posts: 1447
Joined: Mon Oct 19, 2015 12:06 am
Location: Munich, Germany

Re: stm32f429 SRAM + ext SRAM + TFT 16bit with DMA

Post by stevestrong » Tue Jan 24, 2017 4:21 pm

I think this is the setup (taken from STM32 QVGA TFT-LCD drive implementation, AN3241, chapter 2):

Code: Select all

QVGA TFT-LCD signal interfacing with STM32F10xx FSMC

The TFT-LCD synchronization signals VSYNC and HSYNC are managed through STM32 GPIOs.
The FSMC memory interface Write-enable signal is used in inverted configuration as a DCLK (pixel clock) for the TFT,
and the FSMC chip-select signal acts as a TFT-enable signal.
When data is transferred to the FSMC bus, the chip-select is first asserted low to enable the TFT-LCD.
Then the write-enable signal is asserted low to allow 16-bit data transfer to the TFT RGB line on its low level which results in a single pixel display:
■ TFT-Enable: FSMC chip select (pin PG12)
■ VSYNC: GPIO - pin PA8
■ HSYNC: GPIO - pin PC6
■ DCLK: FSMC WE in inverted mode - pin PD5
■ Data Bus: FSMC[D0:D15]
■ SPI1: used for LCD configuration
So there is no need for RS (command/data) switching, you only transfer the whole video buffer from ext. SRAM to TFT via DMA.
And the configuration (window address setting) is most probably done once at the beginning over SPI.

Post Reply

Who is online

Users browsing this forum: No registered users and 1 guest