Execute from external SRAM

Generic boards that are not Maple or Maple mini clones, and don't contain the additional USB reset hardware
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Rick Kimball
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Re: Execute from external SRAM

Postby Rick Kimball » Fri Jan 06, 2017 8:49 pm

I think you need to load the vector table at 0x20000000 for all this to work
-rick

victor_pv
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Re: Execute from external SRAM

Postby victor_pv » Fri Jan 06, 2017 9:28 pm

Pito wrote:After messing with copying the VT from XRAM into IRAM starting at 0x2000FC00 (with top mem 60K in linker), and inspecting entire IRAM on results, I see following:
1. After reset the bootloader starts to fill the addresses from 0x20000000 with VT, where the vectors are all like 0x08xxxxx.
I can step through the bootloader, so I see it fill
2. when I run till next BreakPoint - BP at the very beginning of the LOADER sketch, BP is placed BEFORE I do any copying of .bin to EXRAM, or copying of VT to IRAM (or I commented that out as well) I can see following:
Mem1.JPG

Any idea where it comes from ??????????? - the vectors with 0x68xxxxxx?? They are are in red so it was a change in the debugger.

PS: I've filled out the entire IRAM (20000000-2000FFFF) with 0x00, then done reset.
While running through the bootloader I saw briefly
mem2.JPG


and immediately after the stop at the Breakpoint here:
bp1.JPG

I see the VT at 0x20000000 full of vectors with 0x68s - see above the first picture.. Why?
Could it be it comes from Ozone, or Jlink?? A virus?? :)
The sketch itself works fine, it prints and so on..
:?



You are loading the bin including it in an .h file as a constant or variable, right? that is where it is coming from.
The internal RAM is used by the program in flash to store variables, and in some conditions we have seen it store constants too (pinmap comes to mind, was being stored in RAM despite being a constant).
If you check where the variable or constant for your FSMC bin is in the .map file, I bet it's what's being copied there.
Last edited by victor_pv on Fri Jan 06, 2017 9:32 pm, edited 1 time in total.

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Pito
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Re: Execute from external SRAM

Postby Pito » Fri Jan 06, 2017 9:29 pm

@Rick:
Somebody loads the VT with EXRAM vectors to 0x20000000, but I do not know who. That must be solved first - see my previous post :)
BTw, when briefly played with the APP while VT at 2000FC00 and VTOR=2000FC00 the result was negative - no systick.
But first I have to understand who fills the 0x6x.. vectors to 0x20000000 :) :)
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Pito
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Re: Execute from external SRAM

Postby Pito » Fri Jan 06, 2017 9:32 pm

@Victor: I store it in bin.h

Code: Select all

unsigned char bin[] = {
  0x00, 0xf8, 0x07, 0x68, 0xc9, 0x01, 0x00, 0x68, 0x91, 0x04, 0x00, 0x68,
  0x95, 0x04, 0x00, 0x68, 0x99, 0x04, 0x00, 0x68, 0x9d, 0x04, 0x00, 0x68,
  0xa1, 0x04, 0x00, 0x68, 0xf1, 0x04, 0x00, 0x68, 0xf1, 0x04, 0x00, 0x68,

This code is generated by xxd so I dont mess too much with it. I did in past static const
but never dig into mem.
PS: with

Code: Select all

const static unsigned char bin[] = {
  0x00, 0xf8, 0x07, 0x68, 0xc9, 0x01, 0x00, 0x68, 0x91, 0x04, 0x00, 0x68,
  0x95, 0x04, 0x00, 0x68, 0x99, 0x04, 0x00, 0x68, 0x9d, 0x04, 0x00, 0x68,

mem3.JPG
mem3.JPG (70.83 KiB) Viewed 184 times

Thanks !!!!!!!!!
;)
Last edited by Pito on Fri Jan 06, 2017 9:38 pm, edited 1 time in total.
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victor_pv
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Re: Execute from external SRAM

Postby victor_pv » Fri Jan 06, 2017 9:35 pm

Pito wrote:@Victor: I store it in bin.h

Code: Select all

unsigned char bin[] = {
  0x00, 0xf8, 0x07, 0x68, 0xc9, 0x01, 0x00, 0x68, 0x91, 0x04, 0x00, 0x68,
  0x95, 0x04, 0x00, 0x68, 0x99, 0x04, 0x00, 0x68, 0x9d, 0x04, 0x00, 0x68,
  0xa1, 0x04, 0x00, 0x68, 0xf1, 0x04, 0x00, 0x68, 0xf1, 0x04, 0x00, 0x68,



That "bin" variable is being copied there.
Part of the init copy the liker add to any program, is a small subroutine that will copy initial variable values to an area of RAM.
That area starts from the bottom of the ram address. So there is a few bytes used by other variables, and then the content of the bin[] array.
The .map file should indicate that your bin[] array starts at something like 0x2000000B

EDIT: Does ozone show the addresses in which variables are stored? I bet it does, so should show the same.

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Re: Execute from external SRAM

Postby Pito » Fri Jan 06, 2017 9:44 pm

data.JPG
data.JPG (63.61 KiB) Viewed 183 times

Too much data for a 24" sized display :)
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Re: Execute from external SRAM

Postby Rick Kimball » Fri Jan 06, 2017 9:53 pm

You have to set your boot0=1 and boot1=1, setup your code to store the isr_vector table at 0x20000000 ...
When the cpu resets it maps 0x20000000 to 0x0 ...

Code: Select all

0x0:   0x20005000
(gdb)
0x4:   0x20000109
(gdb) x/i *0x4
   0x20000109 <__vector_table+265>:   ldr.w   pc, [pc, #-264]   ; 0x20000004 <__vector_table+4>

If you look at the normal stm32f103 starup.c code * I'm using the stm32f103c8 * it only maps offset 0, in my case the top of stack at 0x20005000, and offset 0x4 which is the real Reset_Handler we want to run (vector_table+265) (1 word past the last isr vector offset of 0x108)

the ST startup code hardcodes some instructions there ...

Code: Select all

  .equ  BootRAM, 0xF108F85F /* hardcoded instruction */
  /* 0x20000109 <__vector_table+265>: ldr.w pc, [pc, #-264] ; 0x20000004 */

that hardcoded instruction loads the value at 0x2000004 into the PC register and starts running from it. In your case that reset_handler code could be in your 0x60000000 address space, in my case I'm running all this stuff from internal ram.

BTW, I'm not testing with the stm32duino code, I haven't looked how it is setup. The vector table on the stm32f103z is longer so it will have to be different.

Here is gdb session starting up:

Code: Select all

Remote debugging using :3333
0x20000110 in Reset_Handler ()
(gdb) mon reset init
stm32f1x.cpu: target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x20000108 msp: 0x20005000
(gdb) x/2x 0
0x0:   0x20005000   0x20000109
(gdb) x/i *0x4
   0x20000109 <__vector_table+265>:   ldr.w   pc, [pc, #-264]   ; 0x20000004 <__vector_table+4>
(gdb) x/4i *0x20000004
   0x2000010d <Reset_Handler>:   ldr   r0, [pc, #48]   ; (0x20000140 <WWDG_IRQHandler+4>)
   0x2000010f <Reset_Handler+2>:   ldr   r1, [pc, #52]   ; (0x20000144 <WWDG_IRQHandler+8>)
   0x20000111 <Reset_Handler+4>:   ldr   r2, [pc, #52]   ; (0x20000148 <WWDG_IRQHandler+12>)
   0x20000113 <Reset_Handler+6>:   cmp   r1, r2
(gdb) display/i $pc
1: x/i $pc
=> 0x20000110 <Reset_Handler+4>:   ldr   r2, [pc, #52]   ; (0x20000148 <WWDG_IRQHandler+12>)
(gdb) ni
0x2000010c in Reset_Handler ()
1: x/i $pc
=> 0x2000010c <Reset_Handler>:   ldr   r0, [pc, #48]   ; (0x20000140 <WWDG_IRQHandler+4>)
(gdb) ni
0x2000010e in Reset_Handler ()
1: x/i $pc
=> 0x2000010e <Reset_Handler+2>:   ldr   r1, [pc, #52]   ; (0x20000144 <WWDG_IRQHandler+8>)
(gdb) ni
0x20000110 in Reset_Handler ()
1: x/i $pc
=> 0x20000110 <Reset_Handler+4>:   ldr   r2, [pc, #52]   ; (0x20000148 <WWDG_IRQHandler+12>)
(gdb) ni
0x20000112 in Reset_Handler ()
1: x/i $pc
=> 0x20000112 <Reset_Handler+6>:   cmp   r1, r2
(gdb) ni
0x20000114 in Reset_Handler ()
1: x/i $pc
=> 0x20000114 <Reset_Handler+8>:   ittt   cc
(gdb)


EDIT: Here is the stm32f103xb.s code (for bluepill board) I'm running:

Code: Select all

/**
  *************** (C) COPYRIGHT 2016 STMicroelectronics ************************
  * @file      startup_stm32f103xb.s
  * @author    MCD Application Team
  * @version   V4.1.0^1
  * @date      29-April-2016
  * @brief     STM32F103xB Devices vector table for Atollic toolchain.
  *            This module performs:
  *                - Set the initial SP
  *                - Set the initial PC == Reset_Handler,
  *                - Set the vector table entries with the exceptions ISR address
  *                - Configure the clock system
  *                - Branches to main in the C library (which eventually
  *                  calls main()).
  *            After Reset the Cortex-M3 processor is in Thread mode,
  *            priority is Privileged, and the Stack is set to Main.
  ******************************************************************************
  *
  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  *
  * ^1 - rrk modified code to use IT blocks
  */

  .syntax unified
  .cpu cortex-m3
  .thumb

/**
 * @brief  This is the code that gets called when the processor first
 *         starts execution following a reset event.
 *
 *         Note: This code is different from the original ST version (rrk)
 *
 * @param  None
 * @retval : None
*/

  .section .text.Reset_Handler,"ax",%progbits
  .weak Reset_Handler
  .type Reset_Handler, %function

Reset_Handler:

  /* Copy the .data segment initializers from flash to SRAM */
data_init:
  ldr   r0,=_sidata /* start address of initialized data in flash */
  ldr   r1,=_sdata  /* start address of data in SRAM */
  ldr   r2,=_edata  /* end address of data in SRAM */
1:
  cmp   r1,r2
  ittt  lo
  ldrlo r3,[r0],#4
  strlo r3,[r1],#4
  blo.n 1b

  /* Zero fill the .bss segment, assumes aligned on 4 bytes */
bss_init:
  ldr   r0, =_sbss; /* start address of non initialized data in SRAM */
  ldr   r1, =_ebss; /* end address of data in SRAM */
  movs  r2, #0      /* word sized zero constant */
2:
  cmp   r0,r1
  itt   ne
  strne r2,[r0],#4
  bne.n   2b

  /* Configure the HSE/PLL clock system intitialization function.*/
  bl    SystemInit

  /* Call global static constructors, and _init() */
  bl    __libc_init_array

  /* Call the application's entry point.*/
  bl    main


  /* in the unlikely case we do exit main, fall through to Default_Handler */

/**
 * \fn Default_Handler
 * @brief  This is the code that gets called when the processor receives an
 *         unexpected interrupt.  This simply enters an infinite loop, preserving
 *         the system state for examination by a debugger.
 *
 *  Note: this code is probably going to be named using the name of one of
 *  ISR handler function and you won't likely find the name Default_Handler
 *  in the debug strings. Something like this:
 *
 *  (gdb) x/i Default_Handler
 *  0x8000770 <WWDG_IRQHandler>:   b.n   0x8000770 <WWDG_IRQHandler>
 *
 * @param  None
 * @retval : None
 */
  .type Default_Handler, %function
Default_Handler:
  b Default_Handler
  .size Reset_Handler, .-Reset_Handler

  /* try and place linker data here */
  .section .rodata.literal_pool_Reset_Handler,"a",%progbits
  .word _sidata, _sdata, _edata, _sbss, _ebss

  .equ  BootRAM, 0xF108F85F /* hardcoded instruction */
  /* 0x20000109 <__vector_table+265>:   ldr.w   pc, [pc, #-264]   ; 0x20000004 */

/******************************************************************************
* vector table for STM32F10x Medium Density cortex-m3
******************************************************************************/
  .section .isr_vector,"a",%progbits
  .type __vector_table, %object

  /* vector table */
__vector_table:
  /* initial top of stack value */
  .word __stack
  /* exception handlers */
  .word Reset_Handler
  .word NMI_Handler
  .word HardFault_Handler
  .word MemManage_Handler
  .word BusFault_Handler
  .word UsageFault_Handler
  .word 0
  .word 0
  .word 0
  .word 0
  .word SVC_Handler
  .word DebugMon_Handler
  .word 0
  .word PendSV_Handler
  .word SysTick_Handler
#if 1
  /* interrupt handlers */
  .word WWDG_IRQHandler
  .word PVD_IRQHandler
  .word TAMPER_IRQHandler
  .word RTC_IRQHandler
  .word FLASH_IRQHandler
  .word RCC_IRQHandler
  .word EXTI0_IRQHandler
  .word EXTI1_IRQHandler
  .word EXTI2_IRQHandler
  .word EXTI3_IRQHandler
  .word EXTI4_IRQHandler
  .word DMA1_Channel1_IRQHandler
  .word DMA1_Channel2_IRQHandler
  .word DMA1_Channel3_IRQHandler
  .word DMA1_Channel4_IRQHandler
  .word DMA1_Channel5_IRQHandler
  .word DMA1_Channel6_IRQHandler
  .word DMA1_Channel7_IRQHandler
  .word ADC1_2_IRQHandler
  .word USB_HP_CAN1_TX_IRQHandler
  .word USB_LP_CAN1_RX0_IRQHandler
  .word CAN1_RX1_IRQHandler
  .word CAN1_SCE_IRQHandler
  .word EXTI9_5_IRQHandler
  .word TIM1_BRK_IRQHandler
  .word TIM1_UP_IRQHandler
  .word TIM1_TRG_COM_IRQHandler
  .word TIM1_CC_IRQHandler
  .word TIM2_IRQHandler
  .word TIM3_IRQHandler
  .word TIM4_IRQHandler
  .word I2C1_EV_IRQHandler
  .word I2C1_ER_IRQHandler
  .word I2C2_EV_IRQHandler
  .word I2C2_ER_IRQHandler
  .word SPI1_IRQHandler
  .word SPI2_IRQHandler
  .word USART1_IRQHandler
  .word USART2_IRQHandler
  .word USART3_IRQHandler
  .word EXTI15_10_IRQHandler
  .word RTC_Alarm_IRQHandler
  .word USBWakeUp_IRQHandler
  .word 0
  .word 0
  .word 0
  .word 0
  .word 0
  .word 0
  .word 0
  .word BootRAM          /* @0x108. This is for boot in RAM mode for
                            STM32F10x Medium Density devices. */

#endif
  .size __vector_table, .-__vector_table

/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/

  .weak NMI_Handler
  .thumb_set NMI_Handler,Default_Handler

  .weak HardFault_Handler
  .thumb_set HardFault_Handler,Default_Handler

  .weak MemManage_Handler
  .thumb_set MemManage_Handler,Default_Handler

  .weak BusFault_Handler
  .thumb_set BusFault_Handler,Default_Handler

  .weak UsageFault_Handler
  .thumb_set UsageFault_Handler,Default_Handler

  .weak SVC_Handler
  .thumb_set SVC_Handler,Default_Handler

  .weak DebugMon_Handler
  .thumb_set DebugMon_Handler,Default_Handler

  .weak PendSV_Handler
  .thumb_set PendSV_Handler,Default_Handler

  .weak SysTick_Handler
  .thumb_set SysTick_Handler,Default_Handler

  .weak WWDG_IRQHandler
  .thumb_set WWDG_IRQHandler,Default_Handler

  .weak PVD_IRQHandler
  .thumb_set PVD_IRQHandler,Default_Handler

  .weak TAMPER_IRQHandler
  .thumb_set TAMPER_IRQHandler,Default_Handler

  .weak RTC_IRQHandler
  .thumb_set RTC_IRQHandler,Default_Handler

  .weak FLASH_IRQHandler
  .thumb_set FLASH_IRQHandler,Default_Handler

  .weak RCC_IRQHandler
  .thumb_set RCC_IRQHandler,Default_Handler

  .weak EXTI0_IRQHandler
  .thumb_set EXTI0_IRQHandler,Default_Handler

  .weak EXTI1_IRQHandler
  .thumb_set EXTI1_IRQHandler,Default_Handler

  .weak EXTI2_IRQHandler
  .thumb_set EXTI2_IRQHandler,Default_Handler

  .weak EXTI3_IRQHandler
  .thumb_set EXTI3_IRQHandler,Default_Handler

  .weak EXTI4_IRQHandler
  .thumb_set EXTI4_IRQHandler,Default_Handler

  .weak DMA1_Channel1_IRQHandler
  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler

  .weak DMA1_Channel2_IRQHandler
  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler

  .weak DMA1_Channel3_IRQHandler
  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler

  .weak DMA1_Channel4_IRQHandler
  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler

  .weak DMA1_Channel5_IRQHandler
  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler

  .weak DMA1_Channel6_IRQHandler
  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler

  .weak DMA1_Channel7_IRQHandler
  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler

  .weak ADC1_2_IRQHandler
  .thumb_set ADC1_2_IRQHandler,Default_Handler

  .weak USB_HP_CAN1_TX_IRQHandler
  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler

  .weak USB_LP_CAN1_RX0_IRQHandler
  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler

  .weak CAN1_RX1_IRQHandler
  .thumb_set CAN1_RX1_IRQHandler,Default_Handler

  .weak CAN1_SCE_IRQHandler
  .thumb_set CAN1_SCE_IRQHandler,Default_Handler

  .weak EXTI9_5_IRQHandler
  .thumb_set EXTI9_5_IRQHandler,Default_Handler

  .weak TIM1_BRK_IRQHandler
  .thumb_set TIM1_BRK_IRQHandler,Default_Handler

  .weak TIM1_UP_IRQHandler
  .thumb_set TIM1_UP_IRQHandler,Default_Handler

  .weak TIM1_TRG_COM_IRQHandler
  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler

  .weak TIM1_CC_IRQHandler
  .thumb_set TIM1_CC_IRQHandler,Default_Handler

  .weak TIM2_IRQHandler
  .thumb_set TIM2_IRQHandler,Default_Handler

  .weak TIM3_IRQHandler
  .thumb_set TIM3_IRQHandler,Default_Handler

  .weak TIM4_IRQHandler
  .thumb_set TIM4_IRQHandler,Default_Handler

  .weak I2C1_EV_IRQHandler
  .thumb_set I2C1_EV_IRQHandler,Default_Handler

  .weak I2C1_ER_IRQHandler
  .thumb_set I2C1_ER_IRQHandler,Default_Handler

  .weak I2C2_EV_IRQHandler
  .thumb_set I2C2_EV_IRQHandler,Default_Handler

  .weak I2C2_ER_IRQHandler
  .thumb_set I2C2_ER_IRQHandler,Default_Handler

  .weak SPI1_IRQHandler
  .thumb_set SPI1_IRQHandler,Default_Handler

  .weak SPI2_IRQHandler
  .thumb_set SPI2_IRQHandler,Default_Handler

  .weak USART1_IRQHandler
  .thumb_set USART1_IRQHandler,Default_Handler

  .weak USART2_IRQHandler
  .thumb_set USART2_IRQHandler,Default_Handler

  .weak USART3_IRQHandler
  .thumb_set USART3_IRQHandler,Default_Handler

  .weak EXTI15_10_IRQHandler
  .thumb_set EXTI15_10_IRQHandler,Default_Handler

  .weak RTC_Alarm_IRQHandler
  .thumb_set RTC_Alarm_IRQHandler,Default_Handler

  .weak USBWakeUp_IRQHandler
  .thumb_set USBWakeUp_IRQHandler,Default_Handler

/* EOF */

-rick
Last edited by Rick Kimball on Fri Jan 06, 2017 10:05 pm, edited 2 times in total.
-rick

victor_pv
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Re: Execute from external SRAM

Postby victor_pv » Fri Jan 06, 2017 10:02 pm

Pito wrote:
data.JPG

Too much data for a 24" sized display :)


From the map file, doesn't look like it should be that, but from the parts you pasted, looks like the bin starts from address 0x2000000C

In the map file looks like the adc pointers and other stuff starting in 2C.
Are you sure you are compiling the loader code with the correct vector value in the boards file? (should be in the normal flash, the modified only for was for the exRAM bin compilation, which anyway looks like we need to place at 0x20000000)

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Pito
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Location: Rapa Nui

Re: Execute from external SRAM

Postby Pito » Fri Jan 06, 2017 10:11 pm

At this stage I am not sure of anything :)
I will doublecheck, but I think Loader is compiled for original VTOR.
New finding:
1. I set VTOR to 0x2000FC00 in the Loader, I see it at VTOR address correct
2. I jump to APP, stepping a while, VTOR holds
3. Then I run till BP which is set at the beginning of the first delay(3) loop
4. When it stops at that BP the VTOR is changed to 0x08002000..
I have to check the VTOR settings for APP build..

This changes my VTOR:

Code: Select all

/**
 * @brief Initialize the NVIC, setting interrupts to a default priority.
 */
void nvic_init(uint32 address, uint32 offset) {
680006f8:   b510         push   {r4, lr}
 * @param offset Offset from address.  Some restrictions apply to the
 *               use of nonzero offsets; see the ARM Cortex M3
 *               Technical Reference Manual.
 */
void nvic_set_vector_table(uint32 address, uint32 offset) {
    SCB_BASE->VTOR = address | (offset & 0x1FFFFF80);
680006fa:   6098         str   r0, [r3, #8]  <<<<<<<<<<<<<<<<<<<<<<< HERE
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Pito
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Location: Rapa Nui

Re: Execute from external SRAM

Postby Pito » Sat Jan 07, 2017 12:12 am

When inserted the proper VTOR address manually via debugger (see above the issue - the init() messes my VTOR) and continued to step through with its correct value, the delay(3) and delay(2) started to work :ugeek: :ugeek: :ugeek: :ugeek: :ugeek: and the LED toggled. Tired..

2msecs delay.JPG
2msecs delay.JPG (24.43 KiB) Viewed 171 times

delay 3msec.JPG
delay 3msec.JPG (23.35 KiB) Viewed 171 times
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