Designing a new board around existing firmware-F407 vs F417

[Xnke]

As the title explains, I am working on a hardware-port to use existing stocks of STM32F417ZGT6 micros, when the original firmware/coding was for an STM32F407VGT6. I'm pretty green on the STM32, I have built one rather complicated project that works, and now I am picking up an old project that has come back around from when I was interested in it previously.

I found the F417ZGT6's on Ebay, still in packaging from Mouser and Digikey, for less than a buck each. I figure no one else bid because they were searching for F407? Either way, they appear to be genuine and I have a small handful.

Given that both the F407ZGT6 and the F417ZGT6 LQFP-144 devices share the same pinout, I would imagine they would substitute readily, with no hardware and only minor software changes?

If this is the case then the next task will be figuring out the existing pin map vs the new pin map, like when I moved from ATmega2560 to 2561 devices, right?

[fpiSTM]

There is not so much difference btw F407V vs F417Z:

Code: Select all

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<  * Automatically generated from STM32F407V(E-G)Tx.xml, STM32F417V(E-G)Tx.xml
---
>  * Automatically generated from STM32F407Z(E-G)Tx.xml, STM32F417Z(E-G)Tx.xml
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>   {PF_3,      ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9
>   {PF_4,      ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14
>   {PF_5,      ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15
>   {PF_6,      ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
>   {PF_7,      ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5
>   {PF_8,      ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
>   {PF_9,      ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
>   {PF_10,     ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8
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>   {PF_0,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
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>   {PF_1,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
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>   {PF_6,       TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
>   {PF_7,       TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
>   {PF_8,       TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
>   {PF_9,       TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
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>   {PG_14,      USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
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>   {PG_9,       USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
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>   {PG_8,  USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
>   {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
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>   {PG_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
>   {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
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>   {PG_8,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT
>   {PG_11,     ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN
>   {PG_13,     ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0
>   {PG_14,     ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1

Mainly one more ADC, I2C and USART instance. So I guess it is safe and easy to move

[Xnke]

That's what I was thinking-I am glad to see your confirmation.

Thanks a lot!

[saigenku]

From https://www.st.com/en/microcontrollers- ... 7-417.html
"The STM32F417 also integrates a crypto/hash processor providing hardware acceleration for AES 128, 192, 256, Triple DES, and hash (MD5, SHA-1)"