Victor, the 3 outputs of CMOS logic (3.3V) are fed into interrupts inputs - ie PA2, PB3, PA0 (works with any pins with index <= 5, not the same index on several ports).. You know what I mean
There are 360ohm resistors in series in my case. I've put them there to minimize ringing (it may catch more interrupts when it rings). Why it may ring? Because the CMOS outputs are fast and the wires are long, the parasitic LC driven by fast edges rings. The same may happen with encoders, switches etc.
The resistor's value could be higher, as the interrupt's frequency is rather low (max few kilohertz) - thus the RC will not mess too much.
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CMOS ---> 360ohm -----> BPill interrupt input
I am doing that all on a solderless breadboard, all wires 12cm jumping wires.
The PBill's interrupt inputs are configured as INPUTS. No pullups. No capacitors (to be precise - the breadboard's parasitic capacity is 3.5pF/connector2connector and the input capacity of BPill's pin could be 10pF, so ~15pF is the input capacitance).
In the ISRs I do max 1-3 simple instructions ie.
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volatile uint32_t myvar = 0;
volatile uint32_t flag23 = 0;
flag23 = 1;
All interrupts enabled.
PS: when you mess with slow (slow means the signal edges are slower than 10ns) or noisy interrupt signals, I would recommend to condition them via ie. 74HC14 (6 Schmitt trigger inverters) and then continue as above. There are new devices available - 5 pin sot smd pakages, which ie. include only 1 ST inverter http://www.ti.com/lit/ds/symlink/sn74lvc1g14.pdf
(btw look at Fig.8. - a debounce circuit) , so you must not mess with big 14pin packages http://www.ti.com/lit/ds/symlink/sn74hc14.pdf
PSS: I thing the internal pullups pulldowns play no role with "overactive interrupt triggering". My current understanding is, with Libmaple, and 1-2 interrupts triggering 500-2000x per second, with a good triggering signal (good edges, no ringing, no noise) you have to process them without loosing a single interrupt.