Overactive interrupt triggering using internal pullups

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victor_pv
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Re: Overactive interrupt triggering using internal pullups

Post by victor_pv » Mon Sep 18, 2017 7:20 pm

Pito wrote:
Mon Sep 18, 2017 6:38 pm
Btw, I am running here (BPill) 3 attached interrupts at 3 pins, the first fires 1300x per second, the second about 550x, the third about 4-10x per second (all at random times). I am not loosing a single one (so far). In parallel Serial.print(), math, HardWire I2C, bitbanged SPI into Xilinx.
Doing in ISR exactly what you do - incrementing a volatile uint32_t.
Can you post what circuit and settings you are using for debugging if any? (internal pullup, internall pulldown, floating with external resistor of XXohms to 3v3, etc)
That will help a lot as starting point to other people since you are getting good results.

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Re: Overactive interrupt triggering using internal pullups

Post by Pito » Mon Sep 18, 2017 8:05 pm

Victor, the 3 outputs of CMOS logic (3.3V) are fed into interrupts inputs - ie PA2, PB3, PA0 (works with any pins with index <= 5, not the same index on several ports).. You know what I mean :)

There are 360ohm resistors in series in my case. I've put them there to minimize ringing (it may catch more interrupts when it rings). Why it may ring? Because the CMOS outputs are fast and the wires are long, the parasitic LC driven by fast edges rings. The same may happen with encoders, switches etc.

The resistor's value could be higher, as the interrupt's frequency is rather low (max few kilohertz) - thus the RC will not mess too much.

Code: Select all

CMOS ---> 360ohm -----> BPill interrupt input
I am doing that all on a solderless breadboard, all wires 12cm jumping wires.

The PBill's interrupt inputs are configured as INPUTS. No pullups. No capacitors (to be precise - the breadboard's parasitic capacity is 3.5pF/connector2connector and the input capacity of BPill's pin could be 10pF, so ~15pF is the input capacitance).

In the ISRs I do max 1-3 simple instructions ie.

Code: Select all

volatile uint32_t myvar = 0; 
volatile uint32_t flag23 = 0;
my_isr() { 
myvar++;
flag23 = 1;
}
All interrupts enabled.

PS: when you mess with slow (slow means the signal edges are slower than 10ns) or noisy interrupt signals, I would recommend to condition them via ie. 74HC14 (6 Schmitt trigger inverters) and then continue as above. There are new devices available - 5 pin sot smd pakages, which ie. include only 1 ST inverter http://www.ti.com/lit/ds/symlink/sn74lvc1g14.pdf (btw look at Fig.8. - a debounce circuit) , so you must not mess with big 14pin packages http://www.ti.com/lit/ds/symlink/sn74hc14.pdf .

PSS: I thing the internal pullups pulldowns play no role with "overactive interrupt triggering". My current understanding is, with Libmaple, and 1-2 interrupts triggering 500-2000x per second, with a good triggering signal (good edges, no ringing, no noise) you have to process them without loosing a single interrupt.
Last edited by Pito on Mon Sep 18, 2017 8:48 pm, edited 1 time in total.
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octavio
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Re: Overactive interrupt triggering using internal pullups

Post by octavio » Mon Sep 18, 2017 8:48 pm

I get aditionals interrupts without pin changing value, when the button is released and the pin voltage goes slowly (about 200ms) from 0 to 3.3v.Since the interrupt happens without a pin status change,it should be a bug ,not electrical noise.
About volatile: the value is not written out of the ISR and is read on with a single instruction ,so it should not be a problem.

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Pito
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Re: Overactive interrupt triggering using internal pullups

Post by Pito » Mon Sep 18, 2017 8:51 pm

I get aditionals interrupts without pin changing value, when the button is released and the pin voltage goes slowly (about 200ms) from 0 to 3.3v.Since the interrupt happens without a pin status change,it should be a bug ,not electrical noise.
Could you explain me in more detail - what does it mean you get interrupts "without pin changing value" when you also add the input goes "slowly" from zero to 3.3V. Can you clarify it more precisely pls?

If your signal goes slow from 0 to 3.3V in 200ms, you may get 50 additional interrupts. That is because your signal is slow.
The decision level for 1 or 0 in 3.3V CMOS is at 1.65V approximately.
The decision level may change, as the environment is noisy. So you have to spend a minimal time in that region. The logic while at 1.65V will trigger each time the level changes by few millivolts (the changes comes from VCC and GND - it jumps +/- 30mV).
Therefore Schmitt triggers are used - the Schmitt trigger introduces hysteresis - thus a small change at the 1.65V decision level will not retrigger. The BluePill does not have Schmitt triggers at its inputs I think (or does it)? It does have the Schmitt trigger inputs.
https://en.wikipedia.org/wiki/Schmitt_trigger

When somebody wants to chase each and every edge:
1. you must use fast edges (to minimize time spent at 1.65V)
2. or you have to use Schmitt triggers to process slow signals (where the edges are slow)

PS: The Schmitt trigger's hysteresis in BPill is 200mV (datasheet). Hopefully it works. So - when your slow growing signal does not change (while around 1.65V) by 200mV downhill, you have to get 1 interrupt. Anyway, I would recommend to have edges fast.
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Re: Overactive interrupt triggering using internal pullups

Post by Pito » Mon Sep 18, 2017 9:55 pm

@octavio: try to use a different pin for the interrupt, not PA4. Try PA0.
PA4 is SPI1 NSS, you do a remapping of SPI1, maybe there is something weird.
BTW, SPI1 is not at PB3,4,5 by default, but on PA4,5,6,7.
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Re: Overactive interrupt triggering using internal pullups

Post by octavio » Mon Sep 18, 2017 10:05 pm

I mean that the ISR code reads the pin value using "digitalread()" and compares with the value stored in the previous interrupt ,and sometimes is the same,so no interrupt should occur but it happens.And this problem happens while using "Serial.print()", else it works fine.

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Pito
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Re: Overactive interrupt triggering using internal pullups

Post by Pito » Mon Sep 18, 2017 10:07 pm

So pls be so kind and do post your entire code, otherwise we cannot help you..
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RogerClark
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Re: Overactive interrupt triggering using internal pullups

Post by RogerClark » Mon Sep 18, 2017 10:09 pm

in response to a couple of posts...


Steve is correct.. If you dont put a resistor in series with the switch, the surge current to charge the capacitor will cause problems. I experienced this when using a rotary encoder.


@pito.. +1
Supply rail on the BluePill seems quite noisy when I look at it with a scope, and this will potentially cause multiple triggers,

E.g if the i put voltage is from a cap that is slowly charging up, its effectively a high pass filter, and will be a fairly smooth rise.
where as the GPIO input threshold changes all the time as its approx Vcc/2 and Vcc varies slightly all the time.

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Re: Overactive interrupt triggering using internal pullups

Post by Pito » Mon Sep 18, 2017 10:12 pm

We will know more when Octavio will show us the code he actually uses when he experiences issues.
Most probably he has the switch from pin against GND, pullup, and the 10uF capacitor from pin to GND. So he discharges the capacitor to GND, and then he slowly charges it via pullup. So the voltage rises kRC. He is using falling edge, so he fires the interrupt when he presses the button against ground.
Last edited by Pito on Mon Sep 18, 2017 10:30 pm, edited 2 times in total.
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RogerClark
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Re: Overactive interrupt triggering using internal pullups

Post by RogerClark » Mon Sep 18, 2017 10:19 pm

True...

BTW. good call about potential issues with NSS.

Code was added to make it usable as GPIO even when using SPI, and I dont recall anyone having problems with using it as an output.

But there may be problems as an input or with using it as an interrupt pin

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