Dhrystone and Whetstone Benchmarks for STM32F103

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gbulmer
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby gbulmer » Mon Apr 18, 2016 7:58 pm

ddrown wrote:
Here's my stab at doing this: https://gist.github.com/ddrown/3c6de60a ... 4ec350a9ca

...

I can't explain why my math is slower. Maybe the part of the code that I guessed at is different somehow?



Excellent! Yes, that is exactly what I was thinking (but too 'buzy' to do :oops: )

One of my concerns with any benchmarks is being able to reproduce the results; one of the key features of science.

Needed (at least):
  • the entire source code,
  • libraries (or at least library versions),
  • compiler version and compiler flags,
  • linker flags/link script,
  • MCU and clock speed.

The difference may be compiler flags, compiler version, library (different micros?); even the link script can affect the results.

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RogerClark
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Re: Dhrystone and Whetstone Benchmarks for Nucleo STM32L476

Postby RogerClark » Sat Oct 01, 2016 4:19 am

I just ran the test on the Nucleo STM32L476 using STM's new core and I got these figures

Code: Select all

Dhrystone Benchmark, Version 2.1 (Language: C)
Execution starts, 300000 runs through Dhrystone

Execution ends
Microseconds for one run through Dhrystone: 12.20
Dhrystones per Second: 81949.97
VAX MIPS rating = 46.64


Interestingly this is slower than the F103, even though the L476's clock is support to be 8Mhz higher than the 72Mhz F103


At the moment my STM core files for the F103 are in a state of flux, but hopefully I'll be able to try the Nucel F103Rb later (using STM's core)

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martinayotte
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby martinayotte » Sat Oct 01, 2016 2:16 pm

Something wrong here, since my tests done last year with F405 were about 130 VAX MIPS.

So, I presume the system clock still at 8MHz without PLL been started ...

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RogerClark
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby RogerClark » Sat Oct 01, 2016 9:19 pm

There could be a mistake in the core, and it's running at the wrong clock freq.

The spec says this board runs at 80MHz

I don't think the Nucleo have an external 8MHz clock, but someone posted saying that they L4 has some new internal clock which is better than the old RC internal OSC.

I thought I would try SPI on this board, and it did work, but I looked on my logic analyser and the clock was only running at 1MHz , when I just called SPI.begin() .

But I have not checked what the default SPI divider is. I will need to check.

However I see what you mean, as this should be faster than the F103

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Slammer
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby Slammer » Sat Oct 01, 2016 10:19 pm

Yes Roger, in Nucleo L476 Board nothing is connected to XTAL inputs (there is no bridge soldered to connect ST-Link's 8MHz XTAL to target MCU). By default L476 use the MSI clock which is 4MHz, but you can load PLL with it to generate nominal 80 MHz. As I can see in system_stm32l4xx.c file the clock is running at 4MHz but this is strange as this slow speed must be very noticeable in execution of code. ( the clock setup routine must be outside library, normally in variant directory as each board may have different clock setup).

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RogerClark
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby RogerClark » Sun Oct 02, 2016 12:47 am

@slammer

I've not touched the L4 core or variant code at all.

So its running at whatever multipler STM (Wi6Labs set up for it)

I've just taken a quick look at the code in the library (system folder) but I'd need to read the doc's to understand what PLL etc they have setup for this board

But looking at the SPI. If I set DIV64 I get 1Mhz, so this seems to agree with the Dhrystone test which indicate that its probably runing at 64Mhz instead of 80Mhz, I'll see if they have set a 8 x PLL multiplier instead of a 10 x PLL multiplier

Edit

I presume its setup in here

https://github.com/stm32duino/Arduino_C ... tm32l4xx.c

It makes reference to PLL_N being 8, but I can't see where in the code its setting the value of 8. It would be better if they had used Defines or enums for the clock setup stuff, as all I can see are arbitary numbers and various shifting being done

I will email Wi6Labs and STM to find out if they really intended to run this board at what appears to be 64Mhz as the normal spec for the board is 80Mhz

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Slammer
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby Slammer » Sun Oct 02, 2016 9:03 am

Normaly the 4MHz MSI must be devided by PLLM=1 and then with PLLN=40 (x 40) we get 160MHz, finally with PLLR=2 ( / 2) we get 80MHz at the output of PLL.
l4-clock.png
l4-clock.png (37.3 KiB) Viewed 117 times


Normally CubeMX in file system_stm32l4xx.c the default clock is defined (this initialization is common, it is fixed), the user clock configuration is defined in main.c file in function SystemClock_Config.
This is my SystemClock_Config function as generated from CubeMX for Nucle L476 (normally this must be placed somewhere in variant)

Code: Select all

/** System Clock Configuration
*/
void SystemClock_Config(void)
{

  RCC_OscInitTypeDef RCC_OscInitStruct;
  RCC_ClkInitTypeDef RCC_ClkInitStruct;
  RCC_PeriphCLKInitTypeDef PeriphClkInit;

  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
  RCC_OscInitStruct.MSICalibrationValue = 0;
  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
  RCC_OscInitStruct.PLL.PLLM = 1;
  RCC_OscInitStruct.PLL.PLLN = 40;
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }

  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
  {
    Error_Handler();
  }

  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
  PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
  {
    Error_Handler();
  }

  __HAL_RCC_PWR_CLK_ENABLE();

  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
  {
    Error_Handler();
  }

  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);

  HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);

  /* SysTick_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
}

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RogerClark
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby RogerClark » Sun Oct 02, 2016 9:52 am

@slammer

OK.

I just looked in https://github.com/stm32duino/Arduino_C ... w_config.c and I suspect that

Code: Select all

ENABLE_HIGH_SPEED


has not been defined, hence it going to be running at 64Mhz

I suppose I could recompile the Lib, but I've already emailed STM to find out if they intended to run the board on 64Mhz or 80Mhz, because their docs on the board seem to suggest that it should be running at 80MHz

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martinayotte
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby martinayotte » Sun Oct 02, 2016 2:52 pm

RogerClark wrote:I presume its setup in here

https://github.com/stm32duino/Arduino_C ... tm32l4xx.c

In this system_stm32l4xx.c, there PLL is still OFF, and there is no SetSysClock() like in older SPLs such system_stm32f4xx.c.
That explains that this board still running at 8MHz...

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Slammer
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby Slammer » Sun Oct 02, 2016 3:56 pm

In HALMX if you call the SystemCoreClockUpdate function, after call the global variable SystemCoreClock contains the frequency of the active clock in Hz.

@roger and @martinayotte, your notice is correct. The setup of pll is done in hw_config.c file, if the ENABLE_HIGH_SPEED is defined the PLL runs at 4*40/2 =80 MHz else at 4*32/2 = 64 MHz. The functions in system_stm32l4xx.c does not alter anything about clock, there is the SystemCoreClockUpdate function for reading and calculating the frequency of the clock.

Roger try to add the ENABLE_HIGH_SPEED define in building system and test the result, or better the SystemCoreClock variable.
Anyway, I cant see the reason to select the clock between 64MHz and 80MHz, I can understand the selection of a really slow speed (eg 8MHz) for power sensitive applications.


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