Dhrystone and Whetstone Benchmarks for STM32F103

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RogerClark
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby RogerClark » Mon Oct 03, 2016 8:40 pm

Thanks Rick

I have a 100MHz scope, so I will give that a try.

PS. sounds like there is an issue with I2C when the clock is 80mhz, so this board may be limited to 64MHz after all.

But it would be good to sort out this mystery

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RogerClark
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby RogerClark » Mon Oct 03, 2016 9:46 pm

OK

Ran some more tests before and after recompiling the lib

I used the HAL_RCC_GetSysClockFreq() macro, which Fabien (Wi6Labs) emailed me about, to show the clock freq in these tests


Nucleo L476 using STM's core

Code: Select all

Dhrystone Benchmark, Version 2.1 (Language: C)
Clock speed is 80000000
Execution starts, 300000 runs through Dhrystone

Execution ends
Microseconds for one run through Dhrystone: 9.56
Dhrystones per Second: 104628.52
VAX MIPS rating = 59.55



Dhrystone Benchmark, Version 2.1 (Language: C)
Clock speed is 64000000
Execution starts, 300000 runs through Dhrystone

Execution ends
Microseconds for one run through Dhrystone: 11.97
Dhrystones per Second: 83549.77
VAX MIPS rating = 47.55


Maple mini using LibMaple

Code: Select all

Dhrystone Benchmark, Version 2.1 (Language: C)
Execution starts, 300000 runs through Dhrystone

Execution ends
Microseconds for one run through Dhrystone: 11.66
Dhrystones per Second: 85740.84
VAX MIPS rating = 48.80



So the takeaway from this is, that the L4 is more efficient per clock, as a 64Mhz L4 is outperforming a 72Mhz F103

But also that the STM Core is defaulting to 64Mhz where the packaging on the Nucleo box states "80Mhz"

I understand from @grumpyoldpizza that I2C does not work on the L4 at 80Mhz, so I guess people will just need to accept that it runs at 64Mhz, however I can guarantee that this will crop up again when someone buys a nucleo L4 and wonders why its not running at 80Mhz like it says on the box

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Slammer
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby Slammer » Tue Oct 04, 2016 12:47 am

The problem with 80Mhz is by design or requires different setup? I2C timing in L476 is very flexible (and complex), I think that with the proper values in I2C timing registers (and possibly the selection of the clock) it would be possible to have an operating I2C. In mbed for example, the I2C is working while the clock is at 80MHz. I did not check the speed of I2C but I have a working demo with a small OLED screen.

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RogerClark
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby RogerClark » Tue Oct 04, 2016 1:17 am

Thanks @slammer

I have emailed Wi6Labs and STM to say that I think as this board is sold as 80Mhz that the library needs to be compiled so that it does operate at 80MHz, and that the SPI should be 4Mhz (not 1MHz as it is now) and also I2C should be 100kHz when at 80Mhz clock.

I don't know why they chose to use 64Mhz instead of 80Mhz or why SPI is set to 1Mhz when this is not standard even for AVR Arduino boards (Uno etc)

I think STM asked Wi6Labs to make the board run at 80Mhz but perhaps there was a technical reason Wi6Labs decided to use 64MHz

Perhaps Wi6Labs and STM will agree to either use 64 or 80Mhz , as really this is an issue for them to decide.

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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby RogerClark » Tue Oct 04, 2016 3:41 am

Kinda back on topic for a moment

I had to test some nRF51822 code, so thought I may as well run the Drystone test on my nRF51 board, and I got these results

Code: Select all

Dhrystone Benchmark, Version 2.1 (Language: C)
Execution starts, 300000 runs through Dhrystone

Execution ends
Microseconds for one run through Dhrystone: 68.66
Dhrystones per Second: 14564.68
VAX MIPS rating = 8.29


Not surprisingly its considerably slower than the F103, as its only running at 16Mhz, and is less efficient per clock cycle. (I presume this is because its a cortex M0 class device)

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Pito
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby Pito » Tue Oct 04, 2016 7:56 am

Perhaps Wi6Labs and STM will agree to either use 64 or 80Mhz , as really this is an issue for them to decide.

Most probably the L4 at 80MHz is off the marketing's people expectation (ie. power consumption), or it does not run reliably at 80MHz. Otherwise they will set it to 80MHz, I bet. What errata does say?

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RogerClark
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby RogerClark » Tue Oct 04, 2016 10:03 am

From what I was told, STM asked Wi6Labs to program the L476 to run at 80Mhz, as STM sent them the setup code from mbed for 80Mhz, so I think somehow this is a mistake that it only runs at 64Mhz.

The specification of the Nucle L476 definitely says 80Mhz

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Slammer
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby Slammer » Tue Oct 04, 2016 7:18 pm

There is no problem with L476RG at 80MHz, it is working very well. I have used mbed and Chibios in various small tests with I2C, SPI, UARTS etc and is working... I have also select this MCU (best value/price ratio) for a real project (currently on development) with a custom board.

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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby RogerClark » Tue Oct 04, 2016 8:40 pm

STM didnt reply to my email question about what speed they expect it to run at.

I think I will recompile the library and 80Mhz and change the SPI default to DIV 32 which would give 2.5mhz rather than the exiting speed of 1mhz as it should really be 4mhz, but dont think there is a DIV 20 setting. DIV 16 is probably too fast as it would result in 5MHz SPI.

I2C will also need to be adjusted :-(

LMESTM
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Re: Dhrystone and Whetstone Benchmarks for STM32F103

Postby LMESTM » Mon Oct 17, 2016 11:54 am

Hi Roger
I thought I answered to you by email on october 3rd - sorry if I was not clear: yes L476RG will run at 80MHz, This needs to be fixed.
About SPI, why do you think that 5MHz would be too fast vs. 2,5MHz ?
Do we expect issue with some devices if running too fast ?
Cheers
Lauretn


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