[SOLVED] Debug Pins - why use a jtag mode for st-link programming

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zmemw16
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[SOLVED] Debug Pins - why use a jtag mode for st-link programming

Post by zmemw16 » Thu Dec 28, 2017 11:46 pm

@stevestrong wrote in another post-
PB3 and PB4 pins are reserved for the debug interface which is enabled when you upload with STlink.
when i connect to program with a usb st-link block i connect two pins swclk & swdio & gnd of course :)

so as usual, i start up cubemx and played with the sys debug item again, looking at a 103c8
using 2 wire serial, the pins pa13 & pa14 are setup, their naming suggests sys_jtck_swclk & sys_jtms_swdio.
4 wire jtag in addition to above uses pa15 & pb3
5 wire jtag adds on pb4

so the query is why are we setting a jtag mode for st-link ?
why wouldn't we want to just use the minimum pin count we can get away with ?

is there anything extra we can get specifying a jtag mode ?
not with a usb block using 3 wires as i understand it.
my st-link is one of these blue/white egg shaped things:

Code: Select all

0483:3748 STMicroelectronics ST-LINK/V2
has a 20pin connection, so what extras can i get (in my case with a linux system ) ?
no doubt there'll be a dearth for winxx :D
<edit>oops i seem to have inverted the meaning of dearth :lol: </edit>
stephen

stevestrong
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Re: Debug Pins - why use a jtag mode for st-link programming

Post by stevestrong » Fri Dec 29, 2017 8:00 am


zmemw16
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Re: Debug Pins - why use a jtag mode for st-link programming

Post by zmemw16 » Fri Dec 29, 2017 4:30 pm

+1obviously :lol:

actually i'd rather like it if the debug mode could be set in the st-link upload drop down, maybe as swd, jtag4 & jtag5, depending on experience of the user and or their particular hardware. :)
i'm still curious on what if anything we can gain using jtag.
for example; what does seggar do that we can't ?

stephen

zmemw16
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Re: Debug Pins - why use a jtag mode for st-link programming

Post by zmemw16 » Sat Dec 30, 2017 12:05 pm

interestingly the 2017 edition of the cz_ministm32f103v/z boards has esp8266 & nrf24 sockets.
the nrf24 has connections to pb3/pb4/pb5, so obviously i seem to have benefited myself :)
srp
off to read the above pr's

devan
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Re: Debug Pins - why use a jtag mode for st-link programming

Post by devan » Sat Dec 30, 2017 5:57 pm

My understanding is that it is possible to chain the JTAG interfaces of multiple devices together shift-register style so that you can use a single JTAG connector to program / debug any device in the chain. This could be useful for programming a panel of populated boards or if you have a single board with multiple MCUs (ie, one for sensors and one for the radio).

However, I've not tried this myself, so I'm not sure what kind of drawbacks there are besides added complexity. I agree that for virtually all purposes, SWD is superior for debugging ARM MCUs.

zmemw16
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Re: Debug Pins - why use a jtag mode for st-link programming

Post by zmemw16 » Sat Dec 30, 2017 8:12 pm

somewhen in the early 80's, we had a digital logic control board to test ( serious amounts of ttl latches, flip flops, counters, shift registers and simple gates.).
it was sub-contracted out and i can't remember the name of the 'process' though.
essentially bit patterns were generated that exercised every digital path to the outputs.
an inappropriate output would then have further patterns applied in an attempt to isolate the failing device. worst case a series of gates, best the device.

as i understand it, jtag allows prodding of the processors in order exercise them, set or read back some info, but that's not necessarily the same as running the loaded software would do.

stephen

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RogerClark
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Re: Debug Pins - why use a jtag mode for st-link programming

Post by RogerClark » Sat Dec 30, 2017 8:39 pm

stevestrong wrote:
Fri Dec 29, 2017 8:00 am
I agree.
F4 has already the SWD only enabled, see here: https://github.com/rogerclarkmelbourne/ ... ebug.h#L56
PR issued: https://github.com/rogerclarkmelbourne/ ... 2/pull/419
PR.has been merged

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