I was under the impression that normal code would not bother to do that, and that it would happen only when this is configured from the debug configuration that SWD will be used.
If this is not the case, do you happen to know where is this piece of code located? I searched for AFIO_MAPR (this is the register, in which the fields SWJ_CFG[2:0] are controlling the JTAG-SWD configuration) but didn't find anything related in the libraries.
Theses are the bits:
Code: Select all
Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration These bits are write-only (when read, the value is undefined). They are used to configure the SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD access to the Cortex® debug port. The default state after reset is SWJ ON without trace. This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS / JTCK pin. 000: Full SWJ (JTAG-DP + SW-DP): Reset State 001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST 010: JTAG-DP Disabled and SW-DP Enabled 100: JTAG-DP Disabled and SW-DP Disabled Other combinations: no effect