It looks like Wi6Labs wrote the L4 core first

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RogerClark
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It looks like Wi6Labs wrote the L4 core first

Postby RogerClark » Sun Nov 20, 2016 9:35 pm

Looking at the issue we are having with the F1 core, I'm fairly sure that Wi6Labs wrote the L4 core first and the F1 core just a modified copy.

This explains why the RAM usage is high. Because the L4 has loads of RAM hence having 2k structs in RAM that don't need to be, are not a big problem (though this is far from ideal or IMHO 'best practice' for embedded development)

Also We had 2 issues because __HAL_RCC_DAC1_CLK_ENABLE was used, but does not exist on the F1. It should be __HAL_RCC_DAC_CLK_ENABLE

But __HAL_RCC_DAC1_CLK_ENABLE is valid on the L4

https://github.com/stm32duino/Arduino_C ... _hal_rcc.h

Looking at the other STM32 MCU specs, I think the F1 and F0 are probably the least well spec'ed, so are going to be the most problematic for the this HAL based core, as RAM is at a premium.

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Wi6Labs
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Re: It looks like Wi6Labs wrote the L4 core first

Postby Wi6Labs » Wed Nov 23, 2016 9:36 am

Hi Roger,

Indeed we wrote the L4 core first. All the other board are based on it.
Our strategy have been to write a generic source code, easy to understand and to modify. We think our goal is successful, the community have understood quickly the source code. Obviously, the RAM usage is higher because the libstm32f1 is not full optimized.
We agree with you to optimize the RAM usage but do not forget to keep the source code easy to understand and enough generic for all the variant.

BR
Wi6Labs team

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RogerClark
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Re: It looks like Wi6Labs wrote the L4 core first

Postby RogerClark » Wed Nov 23, 2016 7:57 pm

@wi6labs

We are making the code more generic and also simplifying it.


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