FRAM FM24C256 from RAMTRON

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Pito
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Re: FRAM FM24C256 from RAMTRON

Post by Pito » Mon Sep 18, 2017 3:45 pm

Interestingly both papers do not indicate any date the studies/measurements were performed. The NASA and JPL scientists work timeless :)

Date is important as the first FRAMs (especially those smaller) were on market pre-2000. I personally bought an I2C FM24C64 (256kBit similar as the tested in the first paper) in maybe 2000. And that was at least 5y after the FRAM I2C mems introduction.
It could be both papers are 20+y old.

Btw, the Xilinx FPGA used in second paper - the Xilinx FPGAs are known to work reliably up to Mt. Everest altitudes only .. So I would not use them in 10 krads tests :)
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victor_pv
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Re: FRAM FM24C256 from RAMTRON

Post by victor_pv » Mon Sep 18, 2017 4:23 pm

Ramtrom FRAM business is now part of Cypress, so definitely before the date of that acquisition.

One of them is from 2002 for sure, that's the endurance test using the FPGA:
https://ntrs.nasa.gov/search.jsp?R=20060030363

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Pito
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Re: FRAM FM24C256 from RAMTRON

Post by Pito » Mon Sep 18, 2017 4:32 pm

Cypress acquired Ramtron in maybe 2013.
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Re: FRAM FM24C256 from RAMTRON

Post by victor_pv » Mon Sep 18, 2017 5:01 pm

So if the endurance paper is 15 years old, I hope by now they have stopped testing the FRAMs and know how far they actually can go, but didn't publish it!

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Pito
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Re: FRAM FM24C256 from RAMTRON

Post by Pito » Mon Sep 18, 2017 6:02 pm

I discussed with Ramtron guy in 2010/11 and he told me "unlimited".
But, it could happen they discovered the endurance is not such great, and they sold the stuff to Cypress as fast as they could (before the customers start to complain) :lol:
I remember there is a thread in a forum testing endurance of SSD hard drives.
BTW, before I acquired my SSDs, I had observed with interest the web site with online statistics on several SSDs under heavy load.
For people who still think the SSDs wear out fast: the Samsung 850 Pro (I think the 512GB version) did 7PB writes. Its spec says 150TB.
Based on my observation you may count with 5-10x more writes than advertised. With typical amounts of 4-8TB/year (none server usage) such an SSD (usually rated 75-150TB) may last forever :) The same might be applicable to FRAMs too..
Last edited by Pito on Mon Sep 18, 2017 7:24 pm, edited 1 time in total.
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Re: FRAM FM24C256 from RAMTRON

Post by victor_pv » Mon Sep 18, 2017 7:22 pm

Problem with the SSDs was other types of failures that can happen at any time, rather than wear cells. May be the same case with FRAMs, where they will rather give a limit than say unlimited and then see failures because so other parts of the chip fail.

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Pito
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Re: FRAM FM24C256 from RAMTRON

Post by Pito » Mon Sep 18, 2017 7:26 pm

There is the MTBF measure for that. Not sure the FRAM has got some numbers on it in its datasheet..
Here it is for example - the latest FRAM AEC-Q100 Grade 3 Qualification tests from Cypress:
http://www.cypress.com/file/41721/download

TI's FRAMs : data retention 100y, _minimum_ endurance 10^15 writes/erases per cell.
http://www.ti.com/lit/an/slaa526a/slaa526a.pdf
As of 2014:
TI FRAMs Quality.JPG
TI FRAMs Quality.JPG (84.54 KiB) Viewed 218 times
Btw, the endurance of high density flash memories (ie 14-28nm) used in today's SSDs is ~1000(other vendors)-5000(Samsung) writes/erases.
PS: the TI's FRAM technology comes from Ramtron.
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Re: FRAM FM24C256 from RAMTRON

Post by mikikg » Tue Sep 19, 2017 10:06 pm

Another interesting behaviour of mentioned Fujitsu FRAMs regards data signals from it's SO (Slave Output) pin.
Probably this is applicable for other SPI devices but just to mention.

I have an problem when connecting it's SO output pin to some longer SPI line (~25cm), longer mean that it have some larger parasitic capacitance. Parasitic inductance is not relevant for this case.

As this FRAM have very large slew rate on output, when driving large parasitic capacitance it is possible to have "skipped bits", mean that output driver inside FRAM can not drive such line, it's internal current limiter start to activate (in range of few nano seconds) on every rising edge on every transferred logical 1.
It is hard to conclude what is going there because you barely see this on scope, there is no "ringing" or similar expected behaviour, you just see tiny/narrow (needle) pulse instead one bit and MCU usually interpret this as all zeros.

For example, we expect to see 0x55 on SO line and signal should looks like this __|--|__|--|__... but you will see this __|____|___...

Solution for this problem is to put one resistor around 50-150Ω in series close to FRAM's SO pin (we may call this resistor "terminating resistor") to "limit output current" and prevent activation of internal limiter. This will also limit maximum possible transfer rate so take care of that, long lines and high speed do not likes each other ; )

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