IceStamp FPGA in DIL28 and UPduino in DIL32

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martinayotte
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Re: IceStamp FPGA in DIL28 and UPduino in DIL32

Post by martinayotte » Thu Nov 09, 2017 10:04 pm

Pito wrote:
Wed Nov 08, 2017 3:58 pm
@Martin: I've been blinded by your RGB demo (from eevblog) running just now in front of me.. 8-)
The RGB demo I've posted on EEVBlog is only gnarlygrey example modified to have a FSM with 8 colors, it has nothing with the one I've mentioned above with 3x 8bits PWM controlled by I2C slave, which can then fadein/fadeout over million of colors ... ;)

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Pito
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Re: IceStamp FPGA in DIL28 and UPduino in DIL32

Post by Pito » Fri Nov 10, 2017 10:37 pm

The Zylin's ZPU example (but with ~half bram size than the HX8K set in source, needs some fine tuning) fits easily into UPduino

Code: Select all

Logic Resource Utilization:
---------------------------
    Total Logic Cells: 2249/5280
        Combinational Logic Cells: 1558     out of   5280      29.5076%
        Sequential Logic Cells:    691      out of   5280      13.0871%
        Logic Tiles:               349      out of   660       52.8788%
    Registers: 
        Logic Registers:           691      out of   5280      13.0871%
        IO Registers:              0        out of   480       0
    Block RAMs:                    16       out of   30        53.3333%
The UP5k has got 15kB bram, the HX8k 16kB bram. UP5k needs to decode the 0..15kB bram region somehow.. :)
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Rick Kimball
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Re: IceStamp FPGA in DIL28 and UPduino in DIL32

Post by Rick Kimball » Sat Nov 11, 2017 3:51 pm

Pito wrote:
Fri Nov 10, 2017 10:37 pm
The Zylin's ZPU example (but with ~half bram size than the HX8K set in source, needs some fine tuning) fits easily into UPduino
That looks interesting however it seems like development on it has stalled. Is there someplace that talks about that softcore. Everything I found seems to have cooled off in 2015.
-rick

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martinayotte
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Re: IceStamp FPGA in DIL28 and UPduino in DIL32

Post by martinayotte » Sat Nov 11, 2017 4:19 pm

Indeed, interesting !
Especially that I have already played with original AlvieBoy's ZPUino on Xilinx.

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Pito
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Re: IceStamp FPGA in DIL28 and UPduino in DIL32

Post by Pito » Sun Nov 12, 2017 1:22 pm

That looks interesting however it seems like development on it has stalled.
I think that is the tendency nowadays. You can hardly design a better performing sw MCU inside any fpga than are the cheapest hw off-the-shelf offerings today. The designs are therefore either retro computing exercises, or more-less for educational purposes. If you need a sw MCU within your fpga design all those are considered mature. The fpga vendors published their soft MCUs 10y back in average. Moreover, as an improvement, they started to place hw MCUs inside their fpga fabric..
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Rick Kimball
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Re: IceStamp FPGA Board in DIL28

Post by Rick Kimball » Fri Nov 17, 2017 9:43 pm

martinayotte wrote:
Tue Oct 24, 2017 3:40 pm
There is also this one :

http://gnarlygrey.atspace.cc/development-platform.html
Mine just showed up in a plain white envelope .. You can see the holes in the plastic bag where the mail sorter machinary squished it .. * crosses fingers and solders on the pins : )
-rick

zmemw16
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Re: IceStamp FPGA in DIL28 and UPduino in DIL32

Post by zmemw16 » Fri Nov 17, 2017 10:17 pm

yep, white envelope, single wrap of thinnish bubble wrap.
both appear ok.
rather prompt as i was expecting aliexpress travel rates. :)
srp

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Pito
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Re: IceStamp FPGA in DIL28 and UPduino in DIL32

Post by Pito » Sun Nov 19, 2017 1:10 pm

Swapforth J1a running on UPduino (nucleus nuc.fs word set only) @ 24MHz, 115k2 uart, teraterm terminal, built under IceCube2:

Code: Select all

Logic Resource Utilization:
---------------------------
    Total Logic Cells: 1223/5280
        Combinational Logic Cells: 569      out of   5280      10.7765%
        Sequential Logic Cells:    654      out of   5280      12.3864%
        Logic Tiles:               201      out of   660       30.4545%
    Registers: 
        Logic Registers:           654      out of   5280      12.3864%
        IO Registers:              19       out of   480       3.95833
    Block RAMs:                    16       out of   30        53.3333%
  

Code: Select all

  ok
words init .s tasksel quit evaluate refill accept char postpone literal ' abort 
chars char+ cells r@ r> >r depth io@ nip over drop dup swap u< < = invert or and 
xor - + 2/ 2* decimal unloop j i +loop loop ?do leave do recurse does> until again 
then begin if ahead ; exit :noname : [ ] immediate sliteral s, compile, c, , allot 
parse parse-name \ source 2! 2@ cmove> cmove fill >number sfind align um/mod m* * 
um* d2* d0= m+ s>d dabs dnegate d+ aligned /string here abs words forth tth >in 
state base type bounds count c! c@ max min 2over 2swap +! 2dup ?dup 2drop tuck 
-rot rot true false @ execute .x .x2 bl cr space emit key key? rshift lshift io! 
! u> 0> 0< > 0<> <> cell+ 0= 1- negate 1+  ok
  ok
5 5 + .x 000A  ok
  ok
5 5 * .x 0019  ok
  ok
100 100 100 * swap - .x 26AC  ok
  ok
: star 42 emit ;  ok
  ok
: nstar 0 do star loop ;  ok
  ok
16 nstar **************** ok
  ok
Fib2(10000) benchmark @24MHz (https://theultimatebenchmark.org/):

Code: Select all

: fib2 0 1 rot 0 do over + swap loop drop ;
: fib2-bench 10000 0 do i fib2 drop loop ;
fib2-bench  ok
  ok
28secs.
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