Blue Pill running slow

[IanNoob]

OK, I decided that I should put the codes used up here and while knocking the grammar into shape I decided to move the Nano pulses a bit further apart….
It looks as if the ‘Early’ pulses were actually very late ones. Oops sorry.

[IanNoob]

And here is the code:

From GonzoG

Code: Select all

// From https://www.stm32duino.com/viewtopic.php?f=7&t=704&p=4659#p4659  GonzoG IO_speed_test.zip

	#define dWF(a,b) digitalWriteFast(digitalPinToPinName(a),b)
	#define dRF(a) digitalReadFast(digitalPinToPinName(a))

// Modified to use PB3 for read and PB4 for write
#define PIN3r  PB3
#define PIN4w  PB4

void setup() {
  pinMode(PIN3r,INPUT);
  pinMode(PIN4w,OUTPUT);
}
void loop() {
    while ( dRF(PIN3r)){    dWF(PIN4w,1);    dWF(PIN4w,0);}
 }

Asm version 1

Code: Select all

void setup() {
  pinMode(PB4,OUTPUT);
  pinMode(PB3,INPUT);
}
void loop() {
     asm (
    "  ldr.w r0, = #0x40010C08  \n" // GPIOB_IDR  (0x40010C00 + 0x08)) Input Data Register
    "  ldr r2,    = #0x40010C10  \n" // GPIOB_BSRR  (0x40010C00 + 0x10))Bit Set Reset Register 
    "  ldr r3,    = #0x10            \n" // Bit 4 = 0b0001 0000 
    "  ldr r4,    = #0x100000     \n" // Bit 4 = 0b0001 0000 but shifted 16bits higher into   
                                                // Bit 4 = 0b0001 0000 upper (reset) register. See BSRR p173. 
    "aloop:                             \n"      
    "  ldr r1, [r0]          	   \n" // Load contents of IDR to r1
    "  ands r1, r1, #0x08     	  \n" // AND with Set flags against Bit 3 = 0b0000 1000    
    "  beq aloop                	  \n" // Branch if equal to zero (ie, no pulse there)
    "  str r3, [r2]           	  \n" // Set port high
    "  str r4, [r2]          	   \n" // Set port low 
     );                             		// Use C loop() for repeat
    }

Asm 2 version 2

Code: Select all

void setup() {
  pinMode(PB4,OUTPUT);
  pinMode(PB3,INPUT);
}
void loop() {
     asm (
    
    "  ldr.w r0, = #0x40010C08  \n" // GPIOB_IDR  (0x40010C00 + 0x08)) Input Data Register
    "  ldr r2,   = #0x40010C10   \n" // GPIOB_BSRR  (0x40010C00 + 0x10))Bit Set Reset Register 
    "  ldr r3,   = #0x10             \n" // Bit 4 = 0b0001 0000 
    "  ldr r4,   = #0x100000      \n" // Bit 4 = 0b0001 0000 but shifted 16bits higher into   
                                                // Bit 4 = 0b0001 0000 upper (reset) register. See BSRR p173. 
    "aloop:                   	    \n"      
    "  ldr r1, [r0]         	    \n" // Load contents of IDR to r1
    "  ands r1, r1, #0x08    	    \n" // AND with Set flags against Bit 3 = 0b0000 1000
    "  cbz r1, nopulse         	    \n" // CBZ (branch zero) seems better but must branch forwards
    "  str r3, [r2]         	    \n" // Set port high
    "  str r4, [r2]        		     \n" // Set port low
    "nopulse:              	     \n" // CBZ landing point
    "  b aloop             		     \n" // Repeat
     );
    }