WeAct Studio STM32F411CEU6 BlackPill v3.1 crystal is 8 MHz

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Fziegler_076
Posts: 22
Joined: Fri Apr 19, 2024 1:04 am

Re: WeAct Studio STM32F411CEU6 BlackPill v3.1 crystal is 8 MHz

Post by Fziegler_076 »

Arduino IDE 2 have/had issue with menu update. On older version of the IDE (prio 2.3.x), the menu is not refresh at startup.
This could explain your issue.
Thanks for this information, I wouldn't have guessed it myself.




Dear fpiSTM!
If you have the opportunity, please add the BlackPill WeAct Studio STM32F411CE_8MHz board to the new library build, I think many users will need it.

Code: Select all

the hal_conf_extra file is connected.h with the string #define HSE_VALUE 8000000U

and

make changes to the file variant_BLACKPILL_F411CE.cpp
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 192;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 4;
These fixes really work well on this board.
Bingo600
Posts: 87
Joined: Sat Dec 21, 2019 3:56 pm

Re: WeAct Studio STM32F411CEU6 BlackPill v3.1 crystal is 8 MHz

Post by Bingo600 »

Am I totally mistaken here ?
I think i read that choosing a PLLM value where the clock ends up being 2MHz would produce less jitter than selecting one that ends up being 1MHz.

If the above is correct, you might try to redo the Clock/PLL settings before comitting to the repos.

/Bingo

Edit it seems to be correct at least for the F4's

Pg.7 - Secttion 2.2.2
https://www.st.com/resource/en/applicat ... ronics.pdf
2.2.2 Clock scheme for STM32F4xx microcontrollers
This section describes the system clock scheme that is dependent on the voltage
requirements (VDD ) versus the system clock frequency and Flash latency versus the
system clock frequency.
Three different clock sources can be used to drive the system clock (SYSCLK):
1. HSI (16 MHz) oscillator clock
2. HSE (4 MHz to 26 MHz) oscillator clock
3. Main phase-locked loop (PLL) clock with a PLL voltage-controlled oscillator
(PLLVCO) input frequency which must be between1 and 2 MHz (2 MHz is
recommended to limit the PLL jitter) and with division factors M, N, P, and Q.
Suggestion could be:
F4-8MHz-1.png
F4-8MHz-1.png (32.36 KiB) Viewed 51 times
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